1. Technical Field
Embodiments relate to a memory module.
2. Description of the Related Art
As the operating speeds of computer and network systems increase, memories such as dynamic random access memories (DRAMs) require high speed and high capacity. In a computer system, a central processing unit (CPU) may be coupled, e.g., using a memory controller, to a memory such as dynamic random access memory. The memory may be configured as a memory module, which may be inserted into a slot formed on a printed circuit board (PCB) such as a motherboard.
In the memory system, the memory controller and the memory module may be electrically connected through a transmission line formed on the PCB. The operating speed is determined by a data input/output frequency and an operating frequency of a command signal and an address signal. In general, since the command signal and the address signal of the memory system have a larger load than a data signal, a maximum operating frequency may be determined by the command and/or address signal line topology.
As the operating speed of the memory system has increased, the signal line topology has changed to enable high-speed operation. One topology is a fly-by topology. This topology configures channels in the form of a daisy chain and may improve signal line characteristics through impedance matching by connecting loads through a short stub.
The number of loads connected to each signal line of memory modules configured with a plurality of ranks differs according to types of the signal lines. Further, in the fly-by topology, a signal arrival time depends upon the number of loads. Since the number of loads differs according to signal characteristics, a signal transfer time difference occurs according to types of signals.
Since a difference of the signal transfer time from the memory controller to each load increases when the number of loads mounted in the memory module increases, a data setup time and a hold time may be accumulated. Thus, a data window corresponding to a valid interval of delayed and transferred data may be reduced, and skew may cause malfunctions.
In the case of a point-to-point (PTP) connection between memory modules that enables the conventional memory system to operate at high speed, the number of pins of the memory module tends to increase. However, in order to make personal computers and electronic devices compact, lightweight and mechanically efficient, memory modules often cannot be designed to have 250 or more pins. Thus, to meet design limits on the number of pins, the number of memories in the memory module may have to be reduced, resulting in a reduction in data processing capacity.